Analog-to-digital converters (ADCs) typically include one or more sample-and-hold or track-and-hold (T/H) input circuits. The term T/H shall hereinafter refer to either or both sample-and-hold or T/H circuits. A T/H input stage captures the magnitude of an analog signal at a sample time and maintains the sampled amplitude for subsequent quantization and processing.
Some ADCs, including ADCs with fully differential and/or pseudo-differential inputs, may utilize two T/H circuits to capture an analog signal. One T/H circuit captures a (+) phase of the signal and a second, independent T/H circuit captures the (−) phase of the signal.
In the latter case, it is difficult to perfectly match the input impedances of the two T/H circuits. One result of presenting a different input impedance to each input phase is that the resulting composite held signal contains both common-mode and differential signal components. A difference in the input impedances results in imperfect common-mode rejection (CMR). The common-mode component may negatively impact the integrity of the held signal, leading to non-linearity and distortion.
The impact of the mismatch in input impedances increases with increasing frequency, as does the common-mode component of the held signal. Consequently, the problem of decreased CMR resulting from independent T/H inputs may be particularly acute for certain high sampling rate, high frequency applications requiring high levels of linearity.
Another contributor to the common-mode signal on the held inputs is the delay skew between signals appearing on lines of the input differential pair. The delay skew results from path-length differences associated with the separate T/H circuits and associated circuit paths. A result of the input signals not being time-aligned is that the common-mode of the two signals is non-zero and includes the signal itself.
Thus, the amplitude of the common-mode signal relative to the differential signal is a function of the frequency of the analog inputs and the delay skew between the (+) and (−) analog inputs. Higher frequency and/or greater skew result in an increase in common-mode amplitude, a decrease in the apparent amplitude of the differential signal, and a loss of signal-to-noise ratio (SNR).
Existing methods address the problem by attempting to match the delay between the (+) and (−) analog input signals or by changing the delay of the (+) and (−) signals relative to one another. One such method is to use two transformers in a back-to-back relationship in order to improve delay matching of the (+) and (−) analog inputs. Another technique is to use a programmable low-pass filter in series with each (+) and (−) analog input. Input signal delays may be independently tuned by adjusting the time constant of each filter independently. Similarly, wide bandwidth all-pass filters may be used to tune input delays. An alternative technique is to design a system substrate with selectable trace lengths, each having a slightly different propagation delay. A set of trace paths resulting in a reduced differential propagation delay may then be selected.